1. Field of the Invention
The present invention provides a method of forming a capacitor, and more particularly, a method of forming a metal capacitor with two metal electrodes.
2. Description of the Prior Art
In the traditional manufacturing of an analog integrated circuit (IC) chip, top and bottom electrodes of a capacitor are usually made of two polysilicon layers. Since the two polysilicon layers will generate a deplete-region in low voltage operation and induce a serial parasitic capacitor to reduce the effective capacitance, such a capacitor with two polysilicon electrodes can't meet the requirement of low voltage coefficient of capacitance.
Recently, capacitors with two metal electrodes in place of two polysilicon electrodes have been disclosed to increase the capacitance of the capacitor. For example, U.S. Pat. No. 5,479,316 provides a method of forming a capacitor with two metal electrodes, wherein each electrode is made respectively of two metal layers. U.S. Pat. No. 5,086,370 also provides a method of forming a capacitor capable of low-voltage operation. A bottom electrode plate of a TiSi/Poly-Si layer and a top electrode plate of Poly-Si/TiSi layer are used in a capacitor to eliminate the deplete-region and meet the requirement of low voltage coefficient of capacitance.
However, while the requirement of low voltage coefficient of capacitance is met by the methods according to the prior art, either the manufacturing process is very complicated, or, at the very least, an extra metal layers is needed to construct the top/bottom electrodes, which results in a higher cost.